Do not enable SVE on pre-v8.2 platforms

Pre-v8.2 platforms such as the Juno platform does not have
the Scalable Vector Extensions implemented and so the build
option ENABLE_SVE is set to zero.

This has a minor performance improvement with no functional
impact.

Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1
Signed-off-by: David Cunado <[email protected]>

diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 5cd125bff07f9b2b391916f34468dc2403c66ba5..8018b92cd6c07b75ab81f5105cd174568865a8dd 100644 (file)
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -86,6 +86,9 @@ ENABLE_PLAT_COMPAT            :=      0
 # Enable memory map related constants optimisation
 ARM_BOARD_OPTIMISE_MEM         :=      1
 
+# Do not enable SVE
+ENABLE_SVE_FOR_NS              :=      0
+
 include plat/arm/board/common/board_css.mk
 include plat/arm/common/arm_common.mk
 include plat/arm/soc/common/soc_css.mk

diff --git a/plat/compat/plat_compat.mk b/plat/compat/plat_compat.mk
index af885421a65ad8e11e86a1ff812680ecc443070d..f1867da1e6cff22049060bdac4e13cb13785fd65 100644 (file)
--- a/plat/compat/plat_compat.mk
+++ b/plat/compat/plat_compat.mk
@@ -18,3 +18,6 @@ PLAT_BL_COMMON_SOURCES        +=      plat/compat/aarch64/plat_helpers_compat.S
 BL31_SOURCES           +=      plat/common/plat_psci_common.c          \
                                plat/compat/plat_pm_compat.c            \
                                plat/compat/plat_topology_compat.c
+
+# Do not enable SVE
+ENABLE_SVE_FOR_NS      :=      0

diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index 26218a4074fb19843babfe1130dc750802421ae0..18b5e15e0299f83082b9847fd309ad554f60b827 100644 (file)
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk
@@ -24,6 +24,7 @@ PLAT_PARTITION_MAX_ENTRIES    :=      12
 PLAT_PL061_MAX_GPIOS           :=      160
 COLD_BOOT_SINGLE_CPU           :=      1
 PROGRAMMABLE_RESET_ADDRESS     :=      1
+ENABLE_SVE_FOR_NS              :=      0
 
 # Process flags
 $(eval $(call add_define,HIKEY_TSP_RAM_LOCATION_ID))

diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk
index da7bb8254d3947243778e1db5cc8f5cf0c2028aa..695f0923b6384f08b2b90be818d1afcd6edcea17 100644 (file)
--- a/plat/hisilicon/hikey960/platform.mk
+++ b/plat/hisilicon/hikey960/platform.mk
@@ -20,6 +20,7 @@ endif
 CRASH_CONSOLE_BASE             :=      PL011_UART6_BASE
 COLD_BOOT_SINGLE_CPU           :=      1
 PROGRAMMABLE_RESET_ADDRESS     :=      1
+ENABLE_SVE_FOR_NS              :=      0
 
 # Process flags
 $(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID))

diff --git a/plat/hisilicon/poplar/platform.mk b/plat/hisilicon/poplar/platform.mk
index fc75ff353ccad7427f50d534df9f5a0b27b3b596..28e0d1f4fc54c6dcf131431b6af7d939e5cc0544 100644 (file)
--- a/plat/hisilicon/poplar/platform.mk
+++ b/plat/hisilicon/poplar/platform.mk
@@ -13,6 +13,7 @@ ENABLE_PLAT_COMPAT            := 0
 ERRATA_A53_855873              := 1
 ERRATA_A53_835769              := 1
 ERRATA_A53_843419              := 1
+ENABLE_SVE_FOR_NS              := 0
 
 ARM_GIC_ARCH                   := 2
 $(eval $(call add_define,ARM_GIC_ARCH))
@@ -69,4 +70,3 @@ BL31_SOURCES  +=                                                      \
                plat/hisilicon/poplar/bl31_plat_setup.c                 \
                plat/hisilicon/poplar/plat_topology.c                   \
                plat/hisilicon/poplar/plat_pm.c
-

diff --git a/plat/mediatek/mt6795/platform.mk b/plat/mediatek/mt6795/platform.mk
index 4ebc78e57e47c077d52b175d0ef8ea71b18cb262..82300674d475667249df352b7fb1dac726a46137 100644 (file)
--- a/plat/mediatek/mt6795/platform.mk
+++ b/plat/mediatek/mt6795/platform.mk
@@ -66,3 +66,5 @@ PROGRAMMABLE_RESET_ADDRESS    :=      1
 
 $(eval $(call add_define,MTK_SIP_KERNEL_BOOT_ENABLE))
 
+# Do not enable SVE
+ENABLE_SVE_FOR_NS      :=      0

diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk
index cd01645131780c9af914ebf83c71fb0dcefd7e0f..2eef81bb9e16ea30bddf0a05b8250f35230bd374 100644 (file)
--- a/plat/mediatek/mt8173/platform.mk
+++ b/plat/mediatek/mt8173/platform.mk
@@ -70,3 +70,6 @@ ERRATA_A53_855873     :=      1
 PROGRAMMABLE_RESET_ADDRESS     :=      1
 
 $(eval $(call add_define,MTK_SIP_SET_AUTHORIZED_SECURE_REG_ENABLE))
+
+# Do not enable SVE
+ENABLE_SVE_FOR_NS              :=      0

diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk
index 9a9e79e2207e47627786d7cefcc19007d0b946a5..ad60620a4409e6b57645baac1ad95cc53c86c05e 100644 (file)
--- a/plat/nvidia/tegra/platform.mk
+++ b/plat/nvidia/tegra/platform.mk
@@ -29,6 +29,9 @@ SEPARATE_CODE_AND_RODATA :=   1
 # do not use coherent memory
 USE_COHERENT_MEM       :=      0
 
+# do not enable SVE
+ENABLE_SVE_FOR_NS      :=      0
+
 include plat/nvidia/tegra/common/tegra_common.mk
 include ${SOC_DIR}/platform_${TARGET_SOC}.mk
 

diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index 2a7415f58840574c4f1854ead56eb4e00658d6cd..43ab846b49170ca18644eec66a023ae7e6310f60 100644 (file)
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -153,3 +153,6 @@ endif
 
 # Process flags
 $(eval $(call add_define,BL32_RAM_LOCATION_ID))
+
+# Do not enable SVE
+ENABLE_SVE_FOR_NS      :=      0

diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 8863fb4ffc3f465378e6e4fb386962d4791c207e..5de4680e038e045a6439c6c064a7d6488fccb9b1 100644 (file)
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -48,7 +48,10 @@ BL31_SOURCES         +=      ${RK_GIC_SOURCES}                               \
                                ${RK_PLAT_SOC}/drivers/pmu/pmu.c                \
                                ${RK_PLAT_SOC}/drivers/soc/soc.c
 
-ENABLE_PLAT_COMPAT     :=      0
+ENABLE_PLAT_COMPAT     :=      0
 
 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
 $(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))
+
+# Do not enable SVE
+ENABLE_SVE_FOR_NS      :=      0

diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index f6960cf46cad9b305766870329406bf984c88c06..d3c6eeffbc5b5f9ad223c56c6830a52ab93e9a6d 100644 (file)
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -48,6 +48,9 @@ BL31_SOURCES          +=      ${RK_GIC_SOURCES}                               \
                                ${RK_PLAT_SOC}/drivers/soc/soc.c                \
                                ${RK_PLAT_SOC}/drivers/ddr/ddr_rk3368.c         \
 
-ENABLE_PLAT_COMPAT     :=      0
+ENABLE_PLAT_COMPAT     :=      0
 
 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
+
+# Do not enable SVE
+ENABLE_SVE_FOR_NS      :=      0

diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index 6cd5b242a8b37dea0968de24c9bf1a6d63cd2f67..33b9723d7efbbbae7bdb3251a72e31d434f43cac 100644 (file)
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -92,3 +92,6 @@ $(eval $(call MAKE_PREREQ_DIR,${BUILD_M0},${BUILD_PLAT}))
 .PHONY: $(RK3399M0FW)
 $(RK3399M0FW): | ${BUILD_M0}
        $(MAKE) -C ${RK_PLAT_SOC}/drivers/m0 BUILD=$(abspath ${BUILD_PLAT}/m0)
+
+# Do not enable SVE
+ENABLE_SVE_FOR_NS      :=      0

diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index c91abb6be6bd7b9897241da3ecee052a38fc68a8..3c78054b17970d16fbfcc11ded5d1407422d7a01 100644 (file)
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -10,6 +10,7 @@ override ERROR_DEPRECATED     := 1
 override LOAD_IMAGE_V2         := 1
 override USE_COHERENT_MEM      := 1
 override USE_TBBR_DEFS         := 1
+override ENABLE_SVE_FOR_NS     := 0
 
 # Cortex-A53 revision r0p4-51rel0
 # needed for LD20, unneeded for LD11, PXs3 (no ACE)

diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index ca87cc8f1a0694136e216fa5c14fd7e263cd8f80..cb3b44218c7cf2b4cb38dae097a7427ff6a01c4a 100644 (file)
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -11,6 +11,9 @@ A53_DISABLE_NON_TEMPORAL_HINT := 0
 SEPARATE_CODE_AND_RODATA := 1
 override RESET_TO_BL31 := 1
 
+# Do not enable SVE
+ENABLE_SVE_FOR_NS      := 0
+
 ifdef ZYNQMP_ATF_MEM_BASE
     $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))